Publications
2022
2021
2020
2019
2018
2017
2016
2015
2014
2013
2012
2020
2019
2018
2017
2016
2015
2014
2013
2012
2011
2010
2008
These workshop papers are peer-reviewed and have been presented at events, where the proceedings where distributed only among the participants. If you are interested in one of the listed papers, please send me an eMail and I am happy to share the PDF.
2020
Determining the multiplicative complexity of Boolean functions using SAT
Workshop Paper 41
In International Workshop on Logic Synthesis (IWLS) | Salt Lake City, UT, USA, June 2020 | Publisher:
2019
Automatic rreparation of uniform quantum states utilizing Boolean functions
Workshop Paper 40
In International Workshop on Logic Synthesis (IWLS) | Lausanne, Switzerland, June 2019 | Publisher:
ROS: Resource constrained oracle synthesis for quantum computers
Workshop Paper 39
In International Workshop on Logic Synthesis (IWLS) | Lausanne, Switzerland, June 2019 | Publisher:
The complexity of self-dual monotone 7-input functions
Workshop Paper 38
In International Workshop on Logic Synthesis (IWLS) | Lausanne, Switzerland, June 2019 | Publisher:
A hybrid spectral method for checking Boolean function equivalence
Workshop Paper 37
In Reed-Muller Workshop (RM) | Fredericton, NB, Canada, May 2019 | Publisher:
2018
The EPFL logic synthesis libraries
Workshop Paper 36
In Workshop on Open-Source EDA Technology (WOSET) | San Diego, CA, USA, November 2018 | Publisher:
The EPFL logic synthesis libraries
Workshop Paper 35
In International Workshop on Logic Synthesis (IWLS) | San Francisco, CA, USA, June 2018 | Publisher:
Estimating single-target gate T-count using spectral classification
Workshop Paper 34
In International Workshop on Logic Synthesis (IWLS) | San Francisco, CA, USA, June 2018 | Publisher:
Structural rewriting in XOR-majority graphs
Workshop Paper 33
In International Workshop on Logic Synthesis (IWLS) | San Francisco, CA, USA, June 2018 | Publisher:
Normal form systems generated by single connectives have mutually equivalent efficiency
Workshop Paper 32
In Developments in Implicit Computational Complexity (DICE) | Thessaloniki, Greece, April 2018 | Publisher:
2017
Deep learning for logic optimization
Workshop Paper 31
In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, June 2017 | Publisher:
Functional decomposition using majority
Workshop Paper 30
In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, June 2017 | Publisher:
Exact synthesis for logic synthesis applications with complex constraints
Workshop Paper 29
In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, June 2017 | Publisher:
SAT-based optimization with don't-cares revisited
Workshop Paper 28
In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, June 2017 | Publisher:
A compiler for parallel and resource-constrained programmable in-memory computing
Workshop Paper 27
In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, June 2017 | Publisher:
Cut generation for reverse engineering of gate-level netlists
Workshop Paper 26
In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, June 2017 | Publisher:
Boolean function classification with δ-swaps
Workshop Paper 25
In Reed-Muller Workshop (RM) | Novi Sad, Serbia, May 2017 | Publisher:
2016
On the computational complexity of error metrics in approximate computing
Workshop Paper 24
In International Workshop on Boolean Problems (IWSBP) | Freiberg, Germany, September 2016 | Publisher:
LUT mapping and optimization for majority-inverter graphs
Workshop Paper 23
In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, June 2016 | Publisher:
SAT-based functional dependency computation
Workshop Paper 22
In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, June 2016 | Publisher:
Inversion minimization in majority-inverter graphs
Workshop Paper 21
In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, June 2016 | Publisher:
Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications
Workshop Paper 20
In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, June 2016 | Publisher:
Symbolic error metric determination for approximate computing
Workshop Paper 19
In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) | Freiburg, Germany, March 2016 | Pages 75–76 | Publisher:
2015
Simulation graphs for reverse engineering
Workshop Paper 18
In International Workshop on Logic Synthesis (IWLS) | Mountain View, CA, USA, June 2015 | Publisher:
Self-inverse functions and palindromic circuits
Workshop Paper 17
In Reed-Muller Workshop (RM) | Waterloo, ON, Canada, May 2015 | Publisher:
2014
Coverage at the formal specification level
Workshop Paper 16
In International Workshop on Design and Implementation of Formal Tools and Systems (DIFTS) | Lausanne, Switzerland, October 2014 | Publisher:
A framework for reversible circuit complexity
Workshop Paper 15
In International Workshop on Boolean Problems (IWSBP) | Freiberg, Germany, September 2014 | Publisher:
Towards a multi-dimensional and dynamic visualization for ESL designs
Workshop Paper 14
In DATE Friday Workshop: Design Automation for Understanding Hardware Designs (DUHDe) | Dresden, Germany, March 2014 | Publisher:
Formale Methoden für Alle
Workshop Paper 13
In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) | Böblingen, Germany, March 2014 | Pages 213–216 | Publisher:
2013
Law-based verification of complex swarm systems
Workshop Paper 12
In International Workshop on the Swarm at the Edge of the Cloud (SEC) | Montreal, QC, Canada, September 2013 | Publisher:
lips: An IDE for model driven engineering based on natural language processing
Workshop Paper 11
In International Workshop on Natural Language Analysis in Software Engineering (NaturaLiSE) | San Francisco, CA, USA, May 2013 | Publisher:
Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen
Workshop Paper 10
In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) | Rostock, Germany, March 2013 | Pages 99-103 | Publisher:
2012
Verification of embedded systems using modeling and implementation languages
Workshop Paper 9
In International Workshop on and Code Generation for Embedded Systems (MeCoES) | Tampere, Finland, October 2012 | Pages 67–72 | Publisher:
Towards embedding of large functions for reversible logic
Workshop Paper 8
In International Workshop on Boolean Problems (IWSBP) | Freiberg, Germany, September 2012 | Publisher:
2011
Synthesis of reversible circuits with minimal lines for large functions
Workshop Paper 7
In Workshop on Reversible Computation (RC) | Ghent, Belgium, July 2011 | Pages 59–70 | Publisher: Springer
Customized design flows for reversible circuits using RevKit
Workshop Paper 6
In Workshop on Reversible Computation (RC) | Ghent, Belgium, July 2011 | Pages 91–96 | Publisher: Springer
Designing a RISC CPU in reversible logic
Workshop Paper 5
In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) | Oldenburg, Germany, March 2011 | Pages 249–258 | Publisher:
Towards automatic property generation for the formal verification of bus bridges
Workshop Paper 4
In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) | Oldenburg, Germany, March 2011 | Pages 183–192 | Publisher:
2010
RevKit: A toolkit for reversible circuit design
Workshop Paper 3
In Workshop on Reversible Computation (RC) | Bremen, Germany, July 2010 | Pages 69-72 | Publisher: Springer
Hierachical synthesis of reversible circuits using positive and negative Davio decomposition
Workshop Paper 2
In Workshop on Reversible Computation (RC) | Bremen, Germany, July 2010 | Pages 55–58 | Publisher: Springer
Verifying UML/OCL models using Boolean satisfiability
Workshop Paper 1
In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) | Dresden, Germany, March 2010 | Pages 57–66 | Publisher:
Lowering the T-depth of quantum circuits by reducing the multiplicative depth of logic networks
Preprint 20
arXiv:2006.03845 | June 2020
|
Reference
| Comments: 8 pages, 3 figures | Subjects: quant-ph; cs.CR; cs.ET
Quantum circuits for functionally controlled NOT gates
Preprint 19
arXiv:2005.12310 | May 2020
|
Reference
| Comments: 6 pages, 7 figures | Subjects: quant-ph; cs.ET
ROS: resource-constrained oracle synthesis for quantum computers
Preprint 17
arXiv:2005.00211 | May 2020
|
Reference
| Comments: In Proceedings QPL 2019, arXiv:2004.14750 | Subjects: cs.ET; cs.LO; quant-ph
Automatic accuracy management of quantum programs via (near-)symbolic resource estimation
Preprint 16
arXiv:2003.08408 | March 2020
|
Reference
| Comments: 15 pages | Subjects: quant-ph; cs.ET; cs.PL
Improved quantum circuits for elliptic curve discrete logarithms
Preprint 15
arXiv:2001.09580 | January 2020
|
Reference
| Comments: 22 pages, to appear in: Int'l Conf. on Post-Quantum Cryptography (PQCrypto 2020) | Subjects: quant-ph; cs.ET
The role of multiplicative complexity in compiling low T-count oracle circuits
Preprint 14
arXiv:1908.01609 | August 2019
|
Reference
| Comments: 13 pages, 2 tables, 6 figures, To appear in: Proc. Int'l Conf. on Computer-Aided Design (ICCAD 2019) | Subjects: quant-ph; cs.ET
Reversible pebbling game for quantum memory management
Preprint 13
arXiv:1904.02121 | April 2019
|
Reference
| Comments: In Proc. Design Automation and Test in Europe (DATE 2019) | Subjects: quant-ph; cs.ET
Using ZDDs in the mapping of quantum circuits
Preprint 12
arXiv:1901.02406 | January 2019
|
Reference
| Comments: 13 pages, accepted at QPL 2019 | Subjects: quant-ph; cs.ET
Quantum circuits for floating-point arithmetic
Preprint 11
arXiv:1807.02023 | July 2018
|
Reference
| Comments: 13 pages, 2 tables, 6 figures. To appear in: Proc. Reversible Computation (RC 2018) | Subjects: quant-ph; cs.ET
Programming quantum computers using design automation
Preprint 9
arXiv:1803.01022 | March 2018
|
Reference
| Comments: 10 pages, 10 figures | Subjects: quant-ph; cs.ET
Design automation and design space exploration for quantum computers
Preprint 7
arXiv:1612.00631 | December 2016
|
Reference
| Comments: 6 pages, 1 figure | Subjects: quant-ph; cs.ET
Ancilla-free synthesis of large reversible functions using binary decision diagrams
Preprint 4
arXiv:1408.3955 | August 2014
|
Reference
| Comments: 25 pages, 15 figures | Subjects: cs.ET; quant-ph
Embedding of large Boolean functions for reversible logic
Preprint 3
arXiv:1408.3586 | August 2014
|
Reference
| Comments: 13 pages, 10 figures | Subjects: cs.ET
On quantum circuits employing roots of the Pauli matrices
Preprint 1
arXiv:1308.2493 | August 2013
|
Reference
| Comments: 7 pages, 1 figure | Subjects: quant-ph; cs.ET
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