Publications

In press

Logic synthesis for RRAM-based in-memory computing

Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
Journal Article 17 In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Pages | Publisher: IEEE

Exact synthesis of majority-inverter graphs and its applications

Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Journal Article 16 In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Pages | Publisher: IEEE

2017

metaSMT: Focus on your application and not on solver integration

Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey
Journal Article 15 In Journal on Software Tools for Technology Transfer 19(5), 2017 | Pages 605–621 | Publisher: Springer

A PLiM computer for the Internet of Things

Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli
Journal Article 14 In Computer 50(6), 2017 | Pages 35–40 | Publisher: IEEE

2016

Verifying the structure and behavior in UML/OCL models using satisfiability solvers

Nils Przigoda, Mathias Soeken, Robert Wille, Rolf Drechsler
Journal Article 13 In Cyber-Physical Systems: Theory & Applications 1(1), 2016 | Pages 49–59 | Publisher: IET

Time-resolved detection of diffusion limited temperature gradients inside single isolated burning droplets using rainbow refractometry

Christopher D. Rosebrock, Saeideh Shirinzadeh, Mathias Soeken, Norbert Riefler, Thomas Wriedt, Rolf Drechsler, Lutz Mädler
Journal Article 12 In Combustion and Flame 168, 2016 | Pages 255-269 | Publisher: Elsevier

Complexity of reversible circuits and their quantum implementations

Nabila Abdessaied, Matthew Amy, Rolf Drechsler, Mathias Soeken
Journal Article 11 In Theoretical Computer Science 618, 2016 | Pages 85–106 | Publisher: Elsevier

Atomic distributions in crystal structures solved by Boolean satisfiability techniques

Mathias Soeken, Rolf Drechsler, Reinhard X. Fischer
Journal Article 10 In Zeitschrift für Kristallographie - Crystalline Materials 231(2), 2016 | Pages 107–111 | Publisher: De Gruyter

SyReC: A hardware description language for the specification and synthesis of reversible circuits

Robert Wille, Eleonora Schönborn, Mathias Soeken, Rolf Drechsler
Journal Article 9 In Integration 53, 2016 | Pages 39–53 | Publisher: Elsevier

Ancilla-free synthesis of large reversible functions using binary decision diagrams

Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler
Journal Article 8 In Journal of Symbolic Computation 73, 2016 | Pages 1–26 | Publisher: Elsevier

2015

Embedding of large Boolean functions for reversible logic

Mathias Soeken, Robert Wille, Oliver Keszocze, D. Michael Miller, Rolf Drechsler
Journal Article 7 In Journal on Emerging Technologies in Computing Systems 12(4), 2015 | Pages 41 | Publisher: ACM

Specification-driven model transformation testing

Esther Guerra, Mathias Soeken
Journal Article 6 In Software and System Modeling 14(2), 2015 | Pages 623–644 | Publisher: Springer

2014

Upper bounds for reversible circuits based on Young subgroups

Nabila Abdessaied, Mathias Soeken, Michael Kirkedal Thomsen, Rolf Drechsler
Journal Article 5 In Information Processing Letters 114(6), 2014 | Pages 282–286 | Publisher: Elsevier

Trading off circuit lines and gate costs in the synthesis of reversible logic

Robert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler
Journal Article 4 In Integration 47(2), 2014 | Pages 284–294 | Publisher: Elsevier

2013

Quantum circuits employing roots of the Pauli matrices

Mathias Soeken, D. Michael Miller, Rolf Drechsler
Journal Article 3 In Physical Review A 88(042322), 2013 | Pages 042322 | Publisher: American Physical Society

Effect of negative control lines on the exact synthesis of reversible circuits

Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
Journal Article 2 In Multiple-Valued Logic and Soft Computing 21(5--6), 2013 | Pages 627–640 | Publisher: Old City Publishing

2012

RevKit: A toolkit for reversible circuit design

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Journal Article 1 In Multiple-Valued Logic and Soft Computing 18(1), 2012 | Pages 55–65 | Publisher: Old City Publishing

2018

A best-fit mapping algorithm to facilitate ESOP-decomposition in Clifford+T quantum network synthesis

Giulia Meuli, Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli
Conference Paper 91 In Asia and South Pacific Design Automation Conference (ASP-DAC) | Jeju Island, Korea, January 2018 | Publisher: IEEE

Functional decomposition using majority

Zhufei Chu, Mathias Soeken, Yinshui Xia, Giovanni De Micheli
Conference Paper 90 In Asia and South Pacific Design Automation Conference (ASP-DAC) | Jeju Island, Korea, January 2018 | Publisher: IEEE

2017

Enabling exact delay synthesis

Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli
Conference Paper 89 In International Conference on Computer-Aided Design (ICCAD) | Irvine, CA, USA, November 2017 | Publisher: IEEE

Inverter propagation and fan-out constraints for beyond-CMOS majority-based technologies

Eleonora Testa, Odysseas Zografos, Mathias Soeken, Adrien Vaysset, Mauricio Manfrini, Rudy Lauwereins, Giovanni De Micheli
Conference Paper 88 In IEEE Computer Society Annual Symposium on VLSI (ISVLSI) | Bochum, Germany, July 2017 | Publisher: IEEE

An adaptive prioritized ε-preferred evolutionary algorithm for approximate BDD optimization

Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference Paper 87 In Genetic and Evolutionary Computation Conference (GECCO) | Berlin, Germany, July 2017 | Publisher: ACM

Hierarchical reversible logic synthesis using LUTs

Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli
Conference Paper 86 In Design Automation Conference (DAC) | Austin, TX, USA, June 2017 | Publisher: ACM/IEEE

RM3 based logic synthesis

Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Conference Paper 85 In International Symposium on Circuits and Systems (ISCAS) | Baltimore, MD, USA, May 2017 | Publisher: IEEE

Improving circuit mapping performance through MIG-based synthesis for carry chains

Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
Conference Paper 84 In Great Lakes Symposium on VLSI (GLSVLSI) | Banff, AB, Canada, May 2017 | Pages 131-136 | Publisher: ACM

Classifying functions with exact synthesis

Winston Haaswijk, Eleonora Testa, Mathias Soeken, Giovanni De Micheli
Conference Paper 83 In International Symposium on Multiple-Valued Logic (ISMVL) | Novi Sad, Serbia, May 2017 | Publisher: IEEE

Wave pipelining for majority-based beyond-CMOS technologies (invited special session)

Odysseas Zografos, Anton De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amarù, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins
Conference Paper 82 In Design, Automation and Test in Europe (DATE) | Lausanne, Switzerland, March 2017 | Pages 1306-1311 | Publisher: IEEE

Design automation and design space exploration for quantum computers

Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli
Conference Paper 81 In Design, Automation and Test in Europe (DATE) | Lausanne, Switzerland, March 2017 | Pages 470-475 | Publisher: IEEE

Busy Man's Synthesis: Combinational delay optimization with SAT

Mathias Soeken, Giovanni De Micheli, Alan Mishchenko
Conference Paper 80 In Design, Automation and Test in Europe (DATE) | Lausanne, Switzerland, March 2017 | Pages 830-835 | Publisher: IEEE

Endurance management for resistive logic-in-memory computing architectures

Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler
Conference Paper 79 In Design, Automation and Test in Europe (DATE) | Lausanne, Switzerland, March 2017 | Pages 1092-1097 | Publisher: IEEE

Multi-level logic benchmarks: An exactness study

Luca Gaetano Amarù, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Conference Paper 78 In Asia and South Pacific Design Automation Conference (ASP-DAC) | Tokyo, Japan, January 2017 | Pages 157-162 | Publisher: IEEE

A novel basis for logic rewriting

Winston Haaswijk, Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Conference Paper 77 In Asia and South Pacific Design Automation Conference (ASP-DAC) | Tokyo, Japan, January 2017 | Pages 151-156 | Publisher: IEEE

2016

SAT-based combinational and sequential dependency computation

Mathias Soeken, Pascal Raiola, Baruch Sterin, Bernd Becker, Giovanni De Micheli, Matthias Sauer
Conference Paper 76 In Haifa Verification Conference (HVC) | Haifa, Israel, November 2016 | Pages 1-17 | Publisher: Springer

Equivalence checking using Gröbner bases

Amr Sayed Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler
Conference Paper 75 In Formal Methods in Computer-Aided Design (FMCAD) | Mountain View, CA, USA, October 2016 | Pages 169–176 | Publisher: IEEE

Fast hierarchical NPN classification

Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko
Conference Paper 74 In International Conference on Field-Programmable Logic and Applications (FPL) | Lausanne, Switzerland, September 2016 | Pages 1–4 | Publisher: IEEE

Multilevel design understanding: from specification to logic (invited special session)

Sandip Ray, Ian G. Harris, Görschwin Fey, Mathias Soeken
Conference Paper 73 In International Conference on Computer-Aided Design (ICCAD) | Austin, TX, USA, November 2016 | Pages 133 | Publisher: IEEE

Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications

Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne
Conference Paper 72 In International Conference on Computer-Aided Design (ICCAD) | Austin, TX, USA, November 2016 | Pages 4 | Publisher: IEEE

Approximation-aware rewriting of AIGs for error tolerant applications

Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference Paper 71 In International Conference on Computer-Aided Design (ICCAD) | Austin, TX, USA, November 2016 | Pages 83 | Publisher: IEEE

Inversion optimization in majority-inverter graphs

Eleonora Testa, Mathias Soeken, Odysseas Zografos, Luca Gaetano Amarù, Praveen Raghavan, Rudy Lauwereins, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Conference Paper 70 In International Symposium on Nanoscale Architectures (NANOARCH) | Beijing, China, July 2016 | Pages 15–20 | Publisher: IEEE

Heuristic NPN classification for large functions using AIGs and LEXSAT

Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli
Conference Paper 69 In International Conference on Theory and Applications of Satisfiability Testing (SAT) | Bordeaux, France, July 2016 | Pages 212–227 | Publisher: Springer
Best paper candidate

Enumeration of reversible functions and its application to circuit complexity

Mathias Soeken, Nabila Abdessaied, Giovanni De Micheli
Conference Paper 68 In Conference on Reversible Computation (RC) | Bologna, Italy, July 2016 | Pages 255–270 | Publisher: Springer

A fast symbolic transformation based algorithm for reversible logic synthesis

Mathias Soeken, Gerhard W. Dueck, D. Michael Miller
Conference Paper 67 In Conference on Reversible Computation (RC) | Bologna, Italy, July 2016 | Pages 307–321 | Publisher: Springer

Approximate BDD optimization with prioritized ε-preferred evolutionary algorithm

Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference Paper 66 In Genetic and Evolutionary Computation Conference (GECCO) | Denver, CO, USA, July 2016 | Pages 79–80 | Publisher: ACM

An MIG-based compiler for programmable logic-in-memory architectures

Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli
Conference Paper 65 In Design Automation Conference (DAC) | Austin, TX, USA, June 2016 | Pages 117:1–117:6 | Publisher: ACM/IEEE

Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis

Mathias Soeken, Anupam Chattopadhyay
Conference Paper 64 In Design Automation Conference (DAC) | Austin, TX, USA, June 2016 | Pages 149:1–149:6 | Publisher: ACM/IEEE

Precise error determination of approximated components in sequential circuits with model checking

Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference Paper 63 In Design Automation Conference (DAC) | Austin, TX, USA, June 2016 | Pages 129:1–129:6 | Publisher: ACM/IEEE

Technology mapping of reversible circuits to Clifford+T quantum circuits

Nabila Abdessaied, Matthew Amy, Mathias Soeken, Rolf Drechsler
Conference Paper 62 In International Symposium on Multiple-Valued Logic (ISMVL) | Sapporo, Japan, May 2016 | Pages 150–155 | Publisher: IEEE

Notes on majority Boolean algebra

Anupam Chattopadhyay, Luca Gaetano Amarù, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Conference Paper 61 In International Symposium on Multiple-Valued Logic (ISMVL) | Sapporo, Japan, May 2016 | Pages 50–55 | Publisher: IEEE

An extension of transformation-based reversible and quantum circuit synthesis

Mathias Soeken, Gerhard W. Dueck, Md. Mazder Rahman, D. Michael Miller
Conference Paper 60 In International Symposium on Circuits and Systems (ISCAS) | Montreal, QC, Canada, May 2016 | Pages 2290–2293 | Publisher: IEEE

Multi-objective BDD optimization for RRAM based circuit design

Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
Conference Paper 59 In IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) | Košice, Slovakia, April 2016 | Pages 46–15 | Publisher: IEEE

Optimizing majority-inverter graphs with functional hashing

Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Conference Paper 58 In Design, Automation and Test in Europe (DATE) | Dresden, Germany, March 2016 | Pages 1030–1035 | Publisher: IEEE

Fast logic synthesis for RRAM-based in-memory computing using majority-inverter graphs

Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
Conference Paper 57 In Design, Automation and Test in Europe (DATE) | Dresden, Germany, March 2016 | Pages 948–953 | Publisher: IEEE

Formal verification of integer multipliers by combining Gröbner basis with logic reduction

Amr Sayed Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Conference Paper 56 In Design, Automation and Test in Europe (DATE) | Dresden, Germany, March 2016 | Pages 1048–1053 | Publisher: IEEE
Best paper candidate

Dynamic NoC buffer allocation for MPSoC timing side channel attack protection

Johanna Sepulveda, Daniel Florez, Mathias Soeken, Jean-Philippe Diguet, Guy Gogniat
Conference Paper 55 In IEEE Latin Amarican Symposium on Circuits and Systems (LASCAS) | Florianopolis, Brazil, February 2016 | Pages 91–94 | Publisher: IEEE

BDD minimization for approximate computing

Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler
Conference Paper 54 In Asia and South Pacific Design Automation Conference (ASP-DAC) | Macau, China, January 2016 | Pages 474–479 | Publisher: IEEE

2015

Towards an automatic approach for restricting UML/OCL invariability clauses

Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, Rolf Drechsler
Conference Paper 53 In Model-Driven Engineering, Verification, And Validation (MoDeVVa) | Ottawa, ON, Canada, October 2015 | Pages 44–47 | Publisher: ACM

Coverage of OCL operation specifications and invariants

Mathias Soeken, Julia Seiter, Rolf Drechsler
Conference Paper 52 In International Conference on Tests and Proofs (TAP) | L'Aquila, Italy, July 2015 | Pages 191–207 | Publisher: Springer

Reversible circuit rewriting with simulated annealing

Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, Rolf Drechsler
Conference Paper 51 In International Conference on Very Large Scale Integration (VLSI-SoC) | Daejon, Korea, October 2015 | Pages 286–291 | Publisher: IEEE

Ricercar: A language for describing and rewriting reversible circuits with ancillae and its permutation semantics

Michael Kirkedal Thomsen, Robin Kaasgaard Jensen, Mathias Soeken
Conference Paper 50 In Conference on Reversible Computation (RC) | Grenoble, France, July 2015 | Pages 200–215 | Publisher: Springer

Technology mapping for quantum circuits using Boolean functional decomposition

Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
Conference Paper 49 In Conference on Reversible Computation (RC) | Grenoble, France, July 2015 | Pages 219–232 | Publisher: Springer

Reverse engineering with simulation graphs

Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton
Conference Paper 48 In Formal Methods in Computer-Aided Design (FMCAD) | Austin, TX, USA, September 2015 | Pages 152–159 | Publisher: IEEE

Multi-objective BDD optimization with evolutionary algorithms

Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
Conference Paper 47 In Genetic and Evolutionary Computation Conference (GECCO) | Madrid, Spain, July 2015 | Pages 751–758 | Publisher: ACM

Sentence quality assessment based on natural language processing and artificial ingelligence

Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler
Conference Paper 46 In IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) | Belgrad, Serbia, April 2015 | Pages 183–188 | Publisher: IEEE

Fredkin-enabled transformation-based reversible logic synthesis

Mathias Soeken, Anupam Chattopadhyay
Conference Paper 45 In International Symposium on Multiple-Valued Logic (ISMVL) | Waterloo, ON, Canada, May 2015 | Pages 60–65 | Publisher: IEEE

Dynamic template matching with mixed-polarity Toffoli gates

Md. Mazder Rahman, Mathias Soeken, Gerhard W. Dueck
Conference Paper 44 In International Symposium on Multiple-Valued Logic (ISMVL) | Waterloo, ON, Canada, May 2015 | Pages 72–77 | Publisher: IEEE

2014

metaSMT: A unified interface to SMT-LIB2

Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler
Conference Paper 43 In Forum on Specification and Design Languages (FDL) | Munich, Germany, October 2014 | Pages 1–6 | Publisher: IEEE

Automating the translation of assertions using natural language processing techniques

Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris, Rolf Drechsler
Conference Paper 42 In Forum on Specification and Design Languages (FDL) | Munich, Germany, October 2014 | Pages 1–8 | Publisher: IEEE

Self-verification as the key technology for next generation electronic systems

Rolf Drechsler, Hoang M. Le, Mathias Soeken
Conference Paper 41 In Symposium on Integrated Circuits and Systems Design (SBCCI) | Aracaju, Brazil, September 2014 | Pages 15:1–15:4 | Publisher: ACM

Requirements engineering for cyber-physical systems - challenges in the context of "Industrie 4.0"

Stefan Wiesner, Christian Gorldt, Mathias Soeken, Klaus-Dieter Thoben, Rolf Drechsler
Conference Paper 40 In Advances in Production Management Systems (APMS) | Ajaccio, France, September 2014 | Pages 281–288 | Publisher: IFIP

Automated and quality-driven requirements engineering (invited tutorial)

Rolf Drechsler, Mathias Soeken, Robert Wille
Conference Paper 39 In International Conference on Computer-Aided Design (ICCAD) | San Jose, CA, USA, November 2014 | Pages 586–590 | Publisher: IEEE

Behaviour driven development for tests and verification

Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Conference Paper 38 In International Conference on Tests and Proofs (TAP) | York, England, July 2014 | Pages 61–77 | Publisher: Springer

Mapping NCV circuits to optimized Clifford+T circuits

D. Michael Miller, Mathias Soeken, Rolf Drechsler
Conference Paper 37 In Conference on Reversible Computation (RC) | Kyoto, Japan, July 2014 | Pages 163–175 | Publisher: Springer

Quantum circuit optimization by Hadamard gate reduction

Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
Conference Paper 36 In Conference on Reversible Computation (RC) | Kyoto, Japan, July 2014 | Pages 149–162 | Publisher: Springer

2013

Grammar-based program generation based on model finding

Mathias Soeken, Rolf Drechsler
Conference Paper 35 In International Test and Design Symposium (IDT) | Marrakesh, Marocco, December 2013 | Pages 1–5 | Publisher: IEEE

White dots do matter: Rewriting reversible logic circuits

Mathias Soeken, Michael Kirkedal Thomsen
Conference Paper 34 In Conference on Reversible Computation (RC) | Victoria, BC, Canada, July 2013 | Pages 196–208 | Publisher: Springer

Reducing the depth of quantum circuits using additional lines

Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler
Conference Paper 33 In Conference on Reversible Computation (RC) | Victoria, BC, Canada, July 2013 | Pages 221–233 | Publisher: Springer

Hardware-software co-visualization: Developing systems in the holodeck

Rolf Drechsler, Mathias Soeken
Conference Paper 32 In IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) | Karlovy Vary, Czech Republic, April 2013 | Pages 1–4 | Publisher: IEEE

Evaluation of site occupancy factors in crystal structure refinements using Boolean satisfiability techniques

Mathias Soeken, Rolf Drechsler, Reinhard X. Fischer
Conference Paper 31 In Annual Conference of the German Crystallographic Society (DGK) | Freiberg, Germany, March 2013 | Pages 19 | Publisher:

Towards automatic scenario generation from coverage information

Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference Paper 30 In International Workshop on Automation of Software Test (AST) | San Francisco, CA, USA, May 2013 | Pages 82–88 | Publisher: ACM

Debugging of reversible circuits using πDDs

Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler
Conference Paper 29 In International Symposium on Multiple-Valued Logic (ISMVL) | Toyama, Japan, May 2013 | Pages 316–321 | Publisher: IEEE

Exact template matching using Boolean satisfiability

Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler
Conference Paper 28 In International Symposium on Multiple-Valued Logic (ISMVL) | Toyama, Japan, May 2013 | Pages 328–333 | Publisher: IEEE

Determining relevant model elements for the verification of UML/OCL specifications

Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler
Conference Paper 27 In Design, Automation and Test in Europe (DATE) | Grenoble, France, March 2013 | Pages 1189–1192 | Publisher: IEEE

Towards a generic verification methodology for system models

Robert Wille, Martin Gogolla, Mathias Soeken, Mirko Kuhlmann, Rolf Drechsler
Conference Paper 26 In Design, Automation and Test in Europe (DATE) | Grenoble, France, March 2013 | Pages 1193–1196 | Publisher: IEEE

Improving the mapping of reversible circuits to quantum circuits using multiple target lines

Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler
Conference Paper 25 In Asia and South Pacific Design Automation Conference (ASP-DAC) | Yokohama, Japan, January 2013 | Pages 145–150 | Publisher: IEEE

2012

Using πDDs in the design for reversible circuits

Mathias Soeken, Robert Wille, Shin-ichi Minato, Rolf Drechsler
Conference Paper 24 In Conference on Reversible Computation (RC) | Copenhagen, Denmark, July 2012 | Pages 197–203 | Publisher: Springer

Property checking of quantum circuits using quantum multiple-valued decision diagrams

Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler
Conference Paper 23 In Conference on Reversible Computation (RC) | Copenhagen, Denmark, July 2012 | Pages 183–196 | Publisher: Springer

Behavior driven development for circuit design and verification

Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference Paper 22 In International Workshop on High-Level Design Validation and Test (HLDVT) | Huntington Beach, CA, USA, November 2012 | Pages 9–16 | Publisher: IEEE

Completeness-Driven Development

Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille
Conference Paper 21 In International Conference on Graph Transformation (ICGT) | Bremen, Germany, September 2012 | Pages 38–50 | Publisher: Springer

Formal Specification Level: Towards verification-driven design based on natural language processing

Rolf Drechsler, Mathias Soeken, Robert Wille
Conference Paper 20 In Forum on Specification and Design Languages (FDL) | Vienna, Austria, September 2012 | Pages 53–58 | Publisher: IEEE

Circuit line minimization in the HDL-based synthesis of reversible logic

Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler
Conference Paper 19 In IEEE Computer Society Annual Symposium on VLSI (ISVLSI) | Amherst, MA, USA, August 2012 | Pages 213–218 | Publisher: IEEE

Assisted behavior driven development using natural language processing

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference Paper 18 In International Conference on Objects, Models, Components, Patterns (TOOLS) | Prague, Czech Republic, May 2012 | Pages 269–287 | Publisher: Springer

Optimizing the mapping of reversible circuits to four-valued quantum gate circuits

Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler
Conference Paper 17 In International Symposium on Multiple-Valued Logic (ISMVL) | Victoria, BC, Canada, May 2012 | Pages 173–178 | Publisher: IEEE

Exact synthesis of Toffoli gate circuits with negative control lines

Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
Conference Paper 16 In International Symposium on Multiple-Valued Logic (ISMVL) | Victoria, BC, Canada, May 2012 | Pages 69–74 | Publisher: IEEE

A synthesis flow for sequential reversible circuits

Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler
Conference Paper 15 In International Symposium on Multiple-Valued Logic (ISMVL) | Victoria, BC, Canada, May 2012 | Pages 299–304 | Publisher: IEEE

Eliminating invariants in UML/OCL models

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference Paper 14 In Design, Automation and Test in Europe (DATE) | Dresden, Germany, March 2012 | Pages 1142–1145 | Publisher: IEEE

Debugging of inconsistent UML/OCL models

Robert Wille, Mathias Soeken, Rolf Drechsler
Conference Paper 13 In Design, Automation and Test in Europe (DATE) | Dresden, Germany, March 2012 | Pages 1078–1083 | Publisher: IEEE

Synthesis of reversible circuits with minimal lines for large functions

Mathias Soeken, Robert Wille, Nils Przigoda, Christoph Hilken, Rolf Drechsler
Conference Paper 12 In Asia and South Pacific Design Automation Conference (ASP-DAC) | Sydney, Australia, January 2012 | Pages 85–92 | Publisher: IEEE

2011

Towards automatic determination of problem bounds for object instantiation in static model verification

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference Paper 11 In Model-Driven Engineering, Verification, And Validation (MoDeVVa) | Wellington, New Zealand, October 2011 | Pages 2 | Publisher: ACM

Encoding OCL data types for SAT-based verification of UML/OCL models

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference Paper 10 In International Conference on Tests and Proofs (TAP) | Zürich, Switzerland, June 2011 | Pages 152–170 | Publisher: Springer

Automatic property generation for the formal verification of bus bridges

Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Conference Paper 9 In IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) | Cottbus, Germany, April 2011 | Pages 417–422 | Publisher: IEEE

Designing a RISC CPU in reversible logic

Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
Conference Paper 8 In International Symposium on Multiple-Valued Logic (ISMVL) | Tuusula, Finland, May 2011 | Pages 170–175 | Publisher: IEEE

RevKit: An open source toolkit for the design of reversible circuits

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference Paper 7 In Conference on Reversible Computation (RC) | Ghent, Belgium, July 2011 | Pages 65–76 | Publisher: Springer

Verifying dynamic aspects of UML models

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference Paper 6 In Design, Automation and Test in Europe (DATE) | Grenoble, France, March 2011 | Pages 1077–1082 | Publisher: IEEE

2010

Hierarchical synthesis of reversible circuits using positive and negative davio decomposition

Mathias Soeken, Robert Wille, Rolf Drechsler
Conference Paper 5 In International Test and Design Symposium (IDT) | Abu Dhabi, United Arab Emirates, December 2010 | Pages 143–148 | Publisher: IEEE

Reducing the number of lines in reversible circuits

Robert Wille, Mathias Soeken, Rolf Drechsler
Conference Paper 4 In Design Automation Conference (DAC) | Anaheim, CA, USA, June 2010 | Pages 647–652 | Publisher: ACM/IEEE

Window optimization of reversible and quantum circuits

Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Conference Paper 3 In IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) | Vienna, Austria, April 2010 | Pages 341–345 | Publisher: IEEE

Verifying UML/OCL models using Boolean satisfiability

Mathias Soeken, Mirko Kuhlmann, Robert Wille, Martin Gogolla, Rolf Drechsler
Conference Paper 2 In Design, Automation and Test in Europe (DATE) | Dresden, Germany, March 2010 | Pages 1341-1344 | Publisher: IEEE

2008

Using higher levels of abstraction for solving optimization problems by Boolean satisfiability

Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler
Conference Paper 1 In IEEE Computer Society Annual Symposium on VLSI (ISVLSI) | Montpellier, France, April 2008 | Pages 411–416 | Publisher: IEEE

Formal Specification Level

Mathias Soeken, Rolf Drechsler
Book 2 3319086987 | 138 pages | 2014 | Publisher: Springer

Auf dem Weg zum Quantencomputer: Entwurf reversibler Logik (Technische Informatik)

Rolf Drechsler, Mathias Soeken, Robert Wille (Eds.)
Book 1 3844011994 | 226 pages (in German) | 2012 | Publisher: Shaker

These workshop papers are peer-reviewed and have been presented at events, where the proceedings where distributed only among the participants. If you are interested in one of the listed papers, please send me an eMail and I am happy to share the PDF.

2017

Deep learning for logic optimization

Winston Haaswijk, Edo Collins, Benoit Seguin, Mathias Soeken, Sabine Süsstrunk, Frédéric Kaplan, Giovanni De Micheli
Workshop Paper 31 In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, July 2017 | Publisher:

Functional decomposition using majority

Zhufei Chu, Mathias Soeken, Yinshui Xia, Giovanni De Micheli
Workshop Paper 30 In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, July 2017 | Publisher:

Exact synthesis for logic synthesis applications with complex constraints

Eleonora Testa, Mathias Soeken, Odysseas Zografos, Francky Catthoor, Giovanni De Micheli
Workshop Paper 29 In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, July 2017 | Publisher:

SAT-based optimization with don't-cares revisited

Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken
Workshop Paper 28 In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, July 2017 | Publisher:

A compiler for parallel and resource-constrained programmable in-memory computing

Giulia Meuli, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Workshop Paper 27 In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, July 2017 | Publisher:

Cut generation for reverse engineering of gate-level netlists

Baruch Sterin, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton
Workshop Paper 26 In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, July 2017 | Publisher:

Boolean function classification with δ-swaps

Mathias Soeken, Ina Kodrasi, Giovanni De Micheli
Workshop Paper 25 In Reed-Muller Workshop (RM) | Novi Sad, Serbia, May 2017 | Publisher:

2016

On the computational complexity of error metrics in approximate computing

Oliver Keszocze, Mathias Soeken, Rolf Drechsler
Workshop Paper 24 In International Workshop on Boolean Problems (IWSBP) | Freiberg, Germany, September 2016 | Publisher:

LUT mapping and optimization for majority-inverter graphs

Winston Haaswijk, Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Workshop Paper 23 In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, July 2016 | Publisher:

SAT-based functional dependency computation

Mathias Soeken, Pascal Raiola, Baruch Sterin, Matthias Sauer
Workshop Paper 22 In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, July 2016 | Publisher:

Inversion minimization in majority-inverter graphs

Eleonora Testa, Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Workshop Paper 21 In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, July 2016 | Publisher:

Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications

Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne
Workshop Paper 20 In International Workshop on Logic Synthesis (IWLS) | Austin, TX, USA, July 2016 | Publisher:

Symbolic error metric determination for approximate computing

Arun Chandrasekharan, Daniel Große, Mathias Soeken, Rolf Drechsler
Workshop Paper 19 In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) | Freiburg, Germany, March 2016 | Pages 75–76 | Publisher:

2015

Simulation graphs for reverse engineering

Baruch Sterin, Mathias Soeken, Rolf Drechsler, Robert K. Brayton
Workshop Paper 18 In International Workshop on Logic Synthesis (IWLS) | Mountain View, CA, USA, July 2015 | Publisher:

Self-inverse functions and palindromic circuits

Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller
Workshop Paper 17 In Reed-Muller Workshop (RM) | Waterloo, ON, Canada, May 2015 | Publisher:

2014

Coverage at the formal specification level

Rolf Drechsler, Julia Seiter, Mathias Soeken
Workshop Paper 16 In International Workshop on Design and Implementation of Formal Tools and Systems (DIFTS) | Lausanne, Switzerland, October 2014 | Publisher:

A framework for reversible circuit complexity

Mathias Soeken, Nabila Abdessaied, Rolf Drechsler
Workshop Paper 15 In International Workshop on Boolean Problems (IWSBP) | Freiberg, Germany, September 2014 | Publisher:

Towards a multi-dimensional and dynamic visualization for ESL designs

Julia Seiter, Marc Michael, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop Paper 14 In DATE Friday Workshop: Design Automation for Understanding Hardware Designs (DUHDe) | Dresden, Germany, March 2014 | Publisher:

Formale Methoden für Alle

Mathias Soeken, Max Nitze, Rolf Drechsler
Workshop Paper 13 In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) | Böblingen, Germany, March 2014 | Pages 213–216 | Publisher:

2013

Law-based verification of complex swarm systems

Rolf Drechsler, Hoang M. Le, Mathias Soeken, Robert Wille
Workshop Paper 12 In International Workshop on the Swarm at the Edge of the Cloud (SEC) | Montreal, QC, Canada, September 2013 | Publisher:

lips: An IDE for model driven engineering based on natural language processing

Oliver Keszocze, Mathias Soeken, Eugen Kuksa, Rolf Drechsler
Workshop Paper 11 In International Workshop on Natural Language Analysis in Software Engineering (NaturaLiSE) | San Francisco, CA, USA, May 2013 | Publisher:

Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen

Mathias Soeken, Robert Wille, Eugen Kuksa, Rolf Drechsler
Workshop Paper 10 In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) | Rostock, Germany, March 2013 | Pages 99-103 | Publisher:

2012

Verification of embedded systems using modeling and implementation languages

Mathias Soeken, Heinz Riener, Robert Wille, Görschwin Fey, Rolf Drechsler
Workshop Paper 9 In International Workshop on and Code Generation for Embedded Systems (MeCoES) | Tampere, Finland, October 2012 | Pages 67–72 | Publisher:

Towards embedding of large functions for reversible logic

Mathias Soeken, Robert Wille, Laura Tague, D. Michael Miller, Rolf Drechsler
Workshop Paper 8 In International Workshop on Boolean Problems (IWSBP) | Freiberg, Germany, September 2012 | Publisher:

2011

Synthesis of reversible circuits with minimal lines for large functions

Mathias Soeken, Robert Wille, Nils Przigoda, Christoph Hilken, Rolf Drechsler
Workshop Paper 7 In Workshop on Reversible Computation (RC) | Ghent, Belgium, July 2011 | Pages 59–70 | Publisher: Springer

Customized design flows for reversible circuits using RevKit

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Workshop Paper 6 In Workshop on Reversible Computation (RC) | Ghent, Belgium, July 2011 | Pages 91–96 | Publisher: Springer

Designing a RISC CPU in reversible logic

Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
Workshop Paper 5 In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) | Oldenburg, Germany, March 2011 | Pages 249–258 | Publisher:

Towards automatic property generation for the formal verification of bus bridges

Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Workshop Paper 4 In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) | Oldenburg, Germany, March 2011 | Pages 183–192 | Publisher:

2010

RevKit: A toolkit for reversible circuit design

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Workshop Paper 3 In Workshop on Reversible Computation (RC) | Bremen, Germany, July 2010 | Pages 69-72 | Publisher: Springer

Hierachical synthesis of reversible circuits using positive and negative Davio decomposition

Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop Paper 2 In Workshop on Reversible Computation (RC) | Bremen, Germany, July 2010 | Pages 55–58 | Publisher: Springer

Verifying UML/OCL models using Boolean satisfiability

Mathias Soeken, Robert Wille, Mirko Kuhlmann, Martin Gogolla, Rolf Drechsler
Workshop Paper 1 In Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) | Dresden, Germany, March 2010 | Pages 57–66 | Publisher:

Logic synthesis for quantum computing

Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli
Preprint 8 arXiv:1706.02721 | June 2017 | Comments: 15 pages, 10 figures | Subjects: quant-ph; cs.ET

Design automation and design space exploration for quantum computers

Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli
Preprint 7 arXiv:1612.00631 | December 2016 | Reference | Comments: 6 pages, 1 figure | Subjects: quant-ph; cs.ET

Translating between the roots of identity in quantum circuits

Wouter Castryck, Jeroen Demeyer, Alexis De Vos, Oliver Keszocze, Mathias Soeken
Preprint 6 arXiv:1503.08579 | March 2015 | Comments: 7 pages | Subjects: quant-ph; math.GR

Self-inverse functions and palindromic circuits

Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller
Preprint 5 arXiv:1502.05825 | Feburary 2015 | Comments: 6 pages, 3 figures | Subjects: cs.ET; math.GR; quant-ph

Ancilla-free synthesis of large reversible functions using binary decision diagrams

Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler
Preprint 4 arXiv:1408.3955 | August 2014 | Reference | Comments: 25 pages, 15 figures | Subjects: cs.ET; quant-ph

Embedding of large Boolean functions for reversible logic

Mathias Soeken, Robert Wille, Oliver Keszocze, D. Michael Miller, Rolf Drechsler
Preprint 3 arXiv:1408.3586 | August 2014 | Reference | Comments: 13 pages, 10 figures | Subjects: cs.ET

A framework for reversible circuit complexity

Mathias Soeken, Nabila Abdessaied, Rolf Drechsler
Preprint 2 arXiv:1407.5878 | July 2014 | Comments: 6 pages, 4 figures, accepted for Int'l Workshop on Boolean Problems 2014 | Subjects: cs.ET; quant-ph

On quantum circuits employing roots of the Pauli matrices

Mathias Soeken, D. Michael Miller, Rolf Drechsler
Preprint 1 arXiv:1308.2493 | August 2013 | Reference | Comments: 7 pages, 1 figure | Subjects: quant-ph; cs.ET

Copyright Notice

This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.

The following notice applies to all IEEE publications:
IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

The following copyright notice applies to all papers published in the Lecture Notes in Computer Science by Springer-Verlag, as mentionned in the Copyright Form:
The Author may publish his/her contribution on his/her personal Web page provided that he/she creates a link to the above mentioned volume of LNCS at the Springer-Verlag server or to the LNCS series Homepage (URL: http://www.springer.de/comp/lncs/index.html) and that together with this electronic version it is clearly pointed out, by prominently adding "© Springer-Verlag", that the copyright for this contribution is held by Springer.