Invited Talks

2017

Microsoft Research

Talk LUT-based hierarchical reversible logic synthesis invited by Dr. Martin Roetteler and Dr. Nathan Wiebe (February 2017)

2016

Synopsys

Talk SAT-based logic synthesis invited by Dr. Luca Amarù (November 2016)

Microsoft Research

Talk Symbolic and hierarchical reversible logic synthesis invited by Dr. Martin Roetteler and Dr. Nathan Wiebe (September 2016)

Hokkaido University (北海道大学)

Talk Ancilla-free reversible logic synthesis using symbolic methods invited by Prof. Shin-ichi Minato (May 2016)

Banff International Research Station

Talk Ancilla-free reversible logic synthesis using symbolic methods invited by Dr. Martin Roetteler (April 2016)

2015

EPFL (École Polytechnique Fédérale de Lausanne)

Talk Reverse engineering with simulation graphs invited by Prof. Paolo Ienne (June 2015)

Reed-Muller Workshop 2015

Talk Generalized equivalence checking problems for reverse engineering (May 2015)

2014

SRI International

Talk Reverse engineering invited by Dr. Wenchao Li (December 2014)

University of New Brunswick

Talk Formal specification level invited by Prof. Gerhard W. Dueck (October 2014)

Ritsumeikan University (立命館大学)

Talk Formal specification level invited by Prof. Shigeru Yamashita (May 2014)

RWTH Aachen University (RWTH Aachen)

Talk Implementing synthesis flows with RevKit invited by Prof. Anupam Chattopadhyay (2014)

Stanford University

Talk Formal specification level invited by Prof. Subhasish Mitra (April 2014)

2013

CukeUp! 2013

Talk Towards automatic scenario generation based on uncovered code (April 2013)

Hokkaido University (北海道大学)

Talk Synthesis of reversible circuits with minimal lines for large functions invited by Prof. Shin-ichi Minato (January 2013)

2012

CukeUp! 2012

Talk BDD for embedded system design (April 2012)

2011

Hokkaido University (北海道大学)

Talk Formal verification of UML-based specifications invited by Prof. Shin-ichi Minato (January 2011)