Research Interests

  • Logic Synthesis
  • Design Understanding
  • Formal Verification
  • Reversible Logic
  • Quantum Computing

Professional Activities

Organizer: DUHDe 2016, DUHDe 2017

TPC member: DAC 2017, FDL 2014, FDL 2015, FDL 2016 ICCAD 2017, ISMVL 2015, ISMVL 2017, IWLS 2016, IWLS 2017, RC 2016, RC 2017

Others: IWLS 2017 (Contest chair), Reed-Muller 2017 (Publicity chair)


MAJesty: Logic Synthesis with Majority-Inverter Graphs

The MAJesty project aims at developing logic synthesis algorithms and applications based on majority logic. The research is grouped into the three main categories theory, algorithms, and applications. In the theoretical research we want to investigate different forms of majority-based logic and its promising combination with XOR-based logic. In the algorithmic research we develop dedicated approaches tailored for functions of different complexity. As applications we propose synthesis of arithmetic components motivated by results from circuit complexity, threshold logic optimization, inverter optimization, and synthesis for verification. In particular the last application is of high interest, as formal verification is often the bottleneck in today's design flows.

Runtime: to be started (3 years)
Role: Principal Investigator (Co-PI in cooperation with Prof. Giovanni De Micheli, EPFL, Switzerland)

Faster Formal Verification with Reverse Engineering

The project develops new methods for reverse engineering a circuit aiming at increasing the efficiency of formal verification.
Runtime: January 2015 – December 2016
Role: Principal Investigator
Collaborator: Prof. Robert K. Brayton, UC Berkeley, CA, USA

Reversible Computation – Extending Horizons of Computing

This project aims to coordinate the research efforts of European expertise to foster the development in reversible logic for software and hardware and both from a theoretical and practical point of view.
Runtime: April 2015 – April 2019
Role: MC Member